DOCUMENT NO. REV.NO PAGE
STANDARD
`NAME
00 18/20
6.2.6.Function Set
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
001IFN々
BR1 BR2
RS=0, R/W=0 20H to 3FH
々<"Fqp)v"ectg"
This instruction sets width of data bus line.(when to use parallel interface. IM=1). The number of display
line and brightness control.
This instruction initializes the system, and must be the first instruction executed after power-on.
The IF bit selects between an 8-bit or 4-bit bus width interface.
IF=1: 8-bit CPU interface using DB7 to DB0
IF=0: 4-bit CPU interface using DB7 to DB4
The N bit selects between 1-line or 2-line display.
N=1: Select 2 line display (Using anode output A1 to A80)
N=0: Select 1 line display (Using anode output A1 to A40. A41 to A80 fixed Low level.)
BR1, BR0 flag is control to brightness of VFD to modulate pulse width of Anode output as follows.
BR1 BR0 Brightness
0 0 100%
0 1 75%
1 0 50%
1 1 25%
6.2.7 Set CG-RAM Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 1
ACG
RS=0, R/W=0 40H to 7FH
々<"Fqp)v"ectg"
This instruction
(1) Load a new 60bit address into the address counter (ACC).
(2) Sets the address counter (ACC) to address CG-RAM.
Once “Set CG-RAM Address” has been executed, the contents of the address counter (ACC) will be
automatically modified after every access of CG-RAM, as determined by the “Entry Mode Set” instruction.
The active width of the address counter (ACC), when it is addressing CG-RAM, is 6-bit, so the counter will
wrap around to 00H from 3FH if more than 64 bytes of data are written to CG-RAM
6.2.8 Set DD-RAM Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
ADD
RS=0, R/W=0 80H to A7H (1-Line)
C0H to E7h (2-line)
々<"Fqp)v"ectg"
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